1. Field of the Invention
The present invention relates to differential current mode line driver circuits, and in particular, to programmable differential current mode line driver circuits capable of multiple classes of circuit operation.
2. Description of the Related Art
Differential current mode line driver circuits are well known in the art, particularly for use in Ethernet networks such as 100 BASE T and now 1000 BASE T, also known as Gigabit Ethernet (where BASE refers to baseband signaling, and T refers to twisted-pair cabling). Particularly for 1000 BASE T, it is important that multiple drivers be operating in a full duplex mode of operation. Conventional line drivers typically operate in a class A mode in which the current sources are always turned on. This is necessary to avoid ground bounce that often occurs when the current sources are switched on and off at high data rates, and thereby keep distortion low in the output signal waveform. While operation in a class B mode will reduce power consumption, the output data signal will be distorted due to ground bounce introduced by the switching of the current sources.
Accordingly, it would be desirable to have a differential current mode line driver circuit capable of operating in a low distortion, low noise class A mode or a low power class B mode, as desired for the particular application.
In accordance with the presently claimed invention, a programmable differential current mode line driver is provided with multiple classes of circuit operation that can be digitally programmed to operate in a low distortion, low noise class A mode or a low power class B mode, with multiple signal levels available in each mode of operation.
In accordance with one embodiment of the presently claimed invention, a programmable differential current mode line driver with multiple classes of circuit operation includes programmable differential current mode line driver circuitry and control circuitry. The programmable differential current mode line driver circuitry receives a plurality of mode control signals and in response thereto operates in one of a plurality of circuit operation modes and provides a differential current signal with one of a plurality of signal values. The control circuitry, coupled to the programmable differential current mode line driver circuitry, receives a plurality of digital input signals and in response thereto provides the plurality of mode control signals. In response to a first portion of the plurality of digital input signals, the one of a plurality of circuit operation modes includes one of a plurality including a class A circuit operation mode and a class B circuit operation mode. In response to a second portion of the plurality of digital input signals, the one of a plurality of signal values includes one of a plurality including a plurality of positive signal values and a plurality of negative signal values.
In accordance with a more specific embodiment, the programmable differential current mode line driver circuitry further receives a clock signal with a plurality of clock cycles, and the class B circuit operation mode includes a plurality of circuit operation cycles; a precharge cycle during a first portion of the plurality of clock cycles in which the differential current signal becomes a common mode current signal; a hold cycle during a second portion of the plurality of clock cycles in which the differential current signal becomes a differential current signal with the one of the plurality of signal values; and a discharge cycle during a third portion of the plurality of clock cycles in which the differential current signal becomes approximately zero.
In accordance with another embodiment of the presently claimed invention, a method for generating a programmable differential current signal in accordance with multiple classes of circuit operation includes:
receiving a plurality of mode control signals and in response thereto operating in one of a plurality of circuit operation modes and generating a differential current signal with one of a plurality of signal values; and
receiving a plurality of digital input signals and in response thereto generating the plurality of mode control signals, wherein
in response to a first portion of the plurality of digital input signals, the one of a plurality of circuit operation modes includes one of a plurality including a class A circuit operation mode and a class B circuit operation mode, and
in response to a second portion of the plurality of digital input signals, the one of a plurality of signal values includes one of a plurality including a plurality of positive signal values and a plurality of negative signal values.
In accordance with a more specific embodiment, further included is receiving a clock signal with a plurality of clock cycles, and the receiving of a plurality of mode control signals and in response thereto operating in a class B circuit operation mode and generating a differential current signal with one of a plurality of signal values includes:
operating in a precharge cycle during a first portion of the plurality of clock cycles in which the differential current signal becomes a common mode current signal;
operating in a hold cycle during a second portion of the plurality of clock cycles in which the differential current signal becomes a differential current signal with the one of the plurality of signal values; and
operating in a discharge cycle during a third portion of the plurality of clock cycles in which the differential current signal becomes approximately zero.
In accordance with another more specific embodiment, the receiving of a plurality of mode control signals and in response thereto operating in a class B circuit operation mode and generating a differential current signal with one of a plurality of signal values includes:
operating in a precharge cycle during which a common mode current signal is generated;
operating in a hold cycle during which the common mode current signal generated in the precharge cycle becomes a differential signal with one of the plurality of signal values; and
operating in a discharge cycle in which the differential signal generated in the hold cycle becomes another common mode current signal which becomes approximately zero.